While most image sensors can be configured to output a subset of their total resolution, this doesn’t usually lead to energy savings as might have been expected [LiKamWa-2013]. LiKamWa et al. explored energy saving methods possible when using existing sensors, but our project took the idea further by making a new energy-proportional image sensor. Suren Jayasuriya and I did this by adding power gating transistors to the amplifier and ADC in each of the sensor’s readout columns.
As the digital design lead on the project I wrote Verilog RTL to describe a state machine based controller for the rolling-shutter readout and control of the column power gating. I pushed my design through Synopsys synthesis and Suren connected the resulting digital layout to his pixels and other analog circuitry. We taped out this design in IBM’s 130nm technology.